MC74HCT373AN |
RFQ for MC74HCT373AN Required Field |
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| Technical/Catalog Information | MC74HCT373AN |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Logic Type | D-Type Transparent Latch |
| Independent Circuits | 1 |
| Circuit | 8:8 |
| Output Type | Tri-State |
| Current - Output High, Low | 6mA, 6mA |
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (300 mil) |
| Packaging | Tube |
| Operating Temperature | -55°C ~ 125°C |
| Delay Time - Propagation | 28ns |
| Voltage - Supply | 4.5 V ~ 5.5 V |
| Drawing Number | * |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | MC74HCT373AN MC74HCT373AN MC74HCT373ANOS ND MC74HCT373ANOSND MC74HCT373ANOS |
| Product | Manufacturers | Pack | D/C |
| MC74HCT373AN | - | - | 96 |
The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to HighSpeed CMOS inputs. The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent Dtype latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched.
The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled.
The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs.
Features |
| • Output Drive Capability: 15 LSTTL Loads• TTL/NMOSCompatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 V• Low Input Current: 1.0 mA• In Compliance with the Requirements Defined by JEDEC Standard No. 7A• Chip Complexity: 196 FETs or 49 Equivalent Gat |
| Symbol | Parameter | Value | Unit |
| vcc | DC Supply Voltage (Referenced to GND) | 0.5 to +7.0 | V |
| VIN | DC Input Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| VOUT | DC Output Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| LIN | DC Input Current, per Pin | ±20 | mA |
| IOUT | DC Onput Current, per Pin | ±35 | mA |
| ICC | DC Supply Current Per Supply Pin | ±75 | mA |
| PD | Power dissipation in still air piastic DIP SOIC package |
750 500 |
mW |
| TSTG | Storage Temperature | 65 to +150 | °C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 | °C |
